1. Field of the Invention
The invention relates to a method for fabricating a semiconductor device and, more particularly, to a method for fabricating a semiconductor device with a recessed channel.
2. Description of the Related Art
With a drastic decrease in the design rule of integrated circuit semiconductor devices to a level of 70 nm or less, the gate resistance of cell transistors has been greatly increased and the channel length of cell transistors has been markedly decreased. Accordingly, planar transistor structures suffer from limitations in the realization of their gate resistance and threshold voltage. Under such circumstances, a great deal of research has been conducted on methods for ensuring a longer channel length without any increase in design rule. Particularly, studies are actively being undertaken on structures that have an extended channel length while maintaining a limited gate linewidth, for example, semiconductor devices having a recessed channel whose effective channel length is extended by recessing a semiconductor substrate and employing the recessed region as a gate structure.
FIGS. 1 to 8 are cross-sectional views illustrating a method for fabricating a conventional semiconductor device with a recessed channel.
With reference first to FIG. 1, a pad oxide layer 111′ and a pad nitride layer 112′ are sequentially formed on a semiconductor substrate 100 to form a hard mask 110′. As shown in FIG. 2, portions of the surface of the semiconductor substrate 100, particularly isolation regions, are exposed by a common patterning process, leaving a hard mask pattern 110. The hard mask pattern 110 has a structure in which a pad oxide layer pattern 111 and a pad nitride layer pattern 112 are sequentially deposited. Subsequently, etching is conducted using the hard mask pattern 110 as a barrier layer to etch the exposed portions of the semiconductor substrate 100 to a predetermined depth to form trenches 120 for isolation defining an active area 101.
Next, as shown in FIG. 3, a buried insulating layer is deposited on the entire surface of the resulting structure, followed by planarization to form trench isolation layers 122. Then, the hard mask pattern (110 of FIG. 2) is removed. As shown in FIG. 4, a buffer oxide layer 114 is formed on the entire surface of the semiconductor substrate, followed by impurity ion implantation for control of threshold voltage and formation of well/channel. Thereafter, the buffer oxide layer 114 is removed. As shown in FIG. 5, a hard mask 130 including an oxide layer 131 and a polysilicon layer 132 is formed on the semiconductor substrate 100. As shown in FIG. 6, a line-shaped photoresist pattern (not shown) is used to form a hard mask pattern (not shown) through which a recessed region of the semiconductor substrate 100 is exposed. Subsequently, etching is conducted using the hard mask pattern as a barrier layer to etch portions of the semiconductor substrate 100 to a predetermined depth to form trenches 140 for a recessed channel. Then, the hard mask pattern is removed.
As shown in FIG. 7, a gate oxide layer 150 is formed on the entire surface of the semiconductor substrate, and then a polysilicon layer 160, a silicon-rich tungsten silicide layer 170 and a gate hard mask 180 are formed thereon in this order. As shown in FIG. 8, exposed portions of the gate hard mask 180, the silicon-rich tungsten silicide layer 170, the polysilicon layer 160 and the gate oxide layer 150 are removed in this order, leaving gate stacks 190.
The polysilicon layer 160 is grooved due to the presence of the trenches 140 for a recessed channel, as indicated by the sections “A” in FIG. 7. As a result, seams are formed due to poor step coverage of the tungsten silicide (WSix) layer formed during the subsequent step, as indicated by the sections “B” in FIG. 7, resulting in low reliability of the final device. As the tungsten silicide layer is crystallized during a subsequent thermal process, the seams may disappear but the volume of the tungsten silicide layer included under a predetermined gate linewidth is relatively diminished, which increases the resistance of word lines, and as a result, is a cause of reduced operating speed of the final device.
On the other hand, the deposition of the tungsten silicide layer 170 is achieved by chemical vapor deposition (CVD) using WF6 and silane (SiH4) as source gases. In the case where a tungsten-rich tungsten silicide layer is formed instead of the silicon-rich tungsten silicide layer, a reduction in word line resistance can be induced. Specifically, when the flow rate of WF6 introduced into a chamber is increased, a tungsten (W)-rich tungsten silicide layer is formed. The finally crystallized tungsten silicide layer thus formed is relatively thicker than the initially deposited amorphous tungsten silicide layer. The reason for this difference in thickness is that excess tungsten (W) atoms present within the amorphous tungsten silicide layer react with polysilicon present within the underlying polysilicon layer during formation of the tungsten silicide layer by crystallization to form an additional tungsten silicide layer. Accordingly, an increase in the volume of the tungsten silicide layer included in the gate stacks can induce a reduction in word line resistance. However, the content of fluorine (F) components within the amorphous tungsten silicide layer is increased due to the use of the excess WF6 gas, which increases the electrical thickness of the gate insulating layer and causes many problems, such as poor characteristics (e.g., gate oxide integrity (GOI)), making the method unsuitable for practical applications.
At present, since the silicon-rich tungsten silicide layer 170 is formed by relatively increasing the flow rate of silane during CVD to form an amorphous tungsten silicide layer, excess silicon atoms are used to form an additional silicon layer on the polysilicon layer 160, unlike in the formation of the tungsten-rich tungsten silicide layer. As a result, the finally crystallized tungsten silicide layer is relatively thinner than the initially deposited amorphous tungsten silicide layer, which causes an increase in the resistance of word lines.